Automating integrated circuit design with deep learning

Dr. Jason Cong delivered the Jonsson School ‘s annual Distinguished Lecture on AI uses for integrated circuit design for software developers.
When integrated circuits are now created at the smallest scale possible, how can researchers further improve computing applications?
Dr. Jason Cong, professor at the University of California, Los Angeles (UCLA), visited The University of Texas at Dallas in spring 2024 to deliver the Jonsson School’s annual Distinguished Lecture at the Texas Instruments Auditorium.
The lecture was particularly relevant to electrical and computer engineers and to computer science students and has implications for other fields that would incorporate deep learning to speed up extensive or highly technical processes.
“Interacting with renowned faculty of Dr. Cong’s caliber helps us to stay informed and to consider possibilities for our own research,” said Dr. Dinesh Bhatia, professor and head of the Department of Electrical and Computer Engineering at the Erik Jonsson School of Engineering and Computer Science.
Cong is a member of the National Academy of Inventors (NAI) and the National Academy of Engineers (NAE) and has worked as a faculty member for more than 34 years, focusing on integrated circuits, specifically field programmable gate arrays (FPGAs) and related technologies. He is a fellow of the Institute of Electrical and Electronics Engineers (IEEE) and the Association for Computing Machinery (ACM). He also has an h-index of 102, one metric that indicates his significant influence on his field.
“Why would we want to automate chip design?” Cong asked. “This topic has been in the news recently because of concerns about the semiconductor industry supply chain. But also, I think it’s really about the rise of customized computing.”

Jonsson School students working in Dr. Benjamin Carrion Schaefer’s Design Automation and Reconfigurable Computing Laboratory meet one of their heroes. From left are Victoria Gammenthaler, Varun Kuchibhotla, Ojas Suhas Kasbekar, Dr. Jason Cong, Kameswara Pavan Aditya Nukala, Sabrina Ahmed and Baharealsadat Parchamdar.
MOORE’S LAW AND BEYOND
In 1975, Gordon Moore from Intel Inc. predicted that the number of transistors on an integrated circuit would double every two years, and this law has largely remained true for nearly 60 years. Because circuits are now produced at the atomic scale, however, computer engineers have largely reached the physical limit of Moore’s Law. The solution, Cong said, is instead of focusing on fitting as many transistors as possible onto a chip, programmers should create chips that most efficiently meet specific needs depending upon the application, also known as domain-specific computing. As a result, FPGAs were introduced as an off-the-shelf solution that could be configured for specific purposes directly by a software programmer.
Software programmers outnumber computer hardware engineers more than 25 to 1, or roughly 1,795,300 software developers versus 78,100 computer hardware engineers, Cong said. If software developers can safely create and modify chips with precise function specifications, then they can move applications to market much more efficiently, from the C or C++ programming languages to silicon in as little as one day, Cong said. Typical development time for an integrated circuit or IC currently requires up to 18 months.

Attendees listen attentively to the 2024 Jonsson School Distinguished Lecture at the TI Auditorium. Participants include emeritus faculty and graduate students primarily from the Department of Electrical and Computer Engineering.
HIGHER-LEVEL SYNTHESIS TO MACHINE LEARNING
Cong presented a full history of his group’s innovation including in-depth technical details, from their high-level synthesis from 2004 to today. In order to automate the chip design process, Cong and his group considered several methods. They worked systematically, identifying a method of higher-level synthesis (HLS) to use C and C++ as they create the chips.
Cong explained that design bottlenecks would occur frequently, so programmers added a snippet of code called a pragma where they occurred to tell HLS how to overcome the bottlenecks. However, it is time consuming to identify these bottlenecks, and not every software programmer has the knowledge or experience to add the correct pragmas. With deep learning, the system could instead make an educated guess and reduce the time needed to overcome the obstacles.
ChatGPT, a popular chatbot that leverages natural language processing, has largely entered national consciousness. Natural language processing works by synthesizing large amounts of data and producing educated guesses. While ChatGPT generates natural languages or code with ease, it does not have enough training data for integrated circuit design.
Another method, graph neural networks, may be the most appropriate for integrated circuit design, Cong said, largely because HLS is carried out on graphs — specifically the control and data flow graphs — and the GNN models are usually more compact and can be trained with less data. “We don’t need the system to do anything — just give an educated guess,” Cong said.
First, Cong and his team created a database to train the model to identify bottlenecks. Then, they built a predictive model using a single graph neural network encoder across all applications to train the system.
After replacing HLS with a deep learning model, Cong noted that his team was able to speed up the HLS optimization process from hours to milliseconds. The program, HARP, is intended to run with a Merlin compiler to help software programmers.
“Interacting with renowned faculty of Dr. Cong’s caliber helps us to stay informed and to consider possibilities for our own research.”
— Dr. Dinesh Bhatia,
Head and Professor of the Department of Electrical and Computer Engineering

Human intelligence first
“I spent the first part of my career learning to design hardware chips,” Cong said. “There are many architectures, such as systolic array designs, where human intelligence prevails. To do this, we need to have a good understanding of the optimal architecture, the structure design space and the property of optimization problem.”
Jonsson School leaders including Bhatia and Dr. Poras Balsara, vice dean of the Jonsson School and professor of electrical and computer engineering, invited Cong for the lecture.
Balsara has also worked on integrated circuits for his entire career, since the late 1980s. He observed that computer engineers have a fundamental understanding of the chip’s architecture that a software programmer may not possess and may be more adept at troubleshooting due to their familiarity with the technology.
While many questions remain, Cong’s talk illustrates numerous possibilities for technological advancement through deep learning that extends well beyond tools like ChatGPT.
“For those of us who have worked in the areas of electronic design automation and domain-specific architecture design, Dr. Cong has been an inspiration for us for the past 30 years,” said Dr. Benjamin Carrion-Schaefer, assistant dean for graduate student success and professor of electrical and computer engineering, who introduced Cong at the event. “Our colleagues and students especially appreciated visiting one-on-one with Dr. Cong.”
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